Ultrafast shallow-buried-channel CCD's with built-in drift fields

The delay lines are operated with 5-V two-phase clocks, and a potential gradient is permanently built into the storage gates by a step implant in order to improve the charge transfer efficiency (CTE) at high clocking rates. The charge coupled devices (CCDs) with built-in drift fields were tested up to the 325-MHz limit of the existing clock drivers with no degradation in the CTE(>0.99996), while the equivalent CCDs with uniformly doped storage wells degrade rapidly above 240 MHz. These results are consistent with two-dimensional computer simulations