Comment on `Nonplanar VLSI arrays with high fault-tolerancecapabilities'

In the above-named work (see ibid., vol.38, p.51-7, April 1989), S. Lafiti and A. El-Amawy apply, in a straightforward manner, the method developed by A.D. Singh (1985) to calculate lower bounds for the yield of nonplanar interstitial redundancy topologies of processor arrays with spare processors. In their introduction, they claim that the models suggested by I. Koren and D.K. Pradhan (1987) are highly theoretical since the number of states in the Markov model might be very large and the determination of the transition rates might be intractable. They add that applying some empirical rules, as suggested by Koren and Pradhan (1987), can lead to unrealistic results and may require a large number of computations. They also claim that the model of Koren and Pradhan does not suggest an algorithm to replace faulty elements. They conclude that a simpler model, like the one proposed by Singh, is needed for calculating the yield of fault-tolerant processor arrays. In the present comment, Koren and Pradhan respond to the above comments and attempt to clarify the differences between their yield analysis and that of Singh