| 基于RLC模型的互连线时延估算 |
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| 引用本文： | 李朝辉,孙玉楠.基于RLC模型的互连线时延估算[J].计算机工程与设计,2008,29(20). |
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| 作者姓名： | 李朝辉 孙玉楠 |
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| 作者单位： | 1. 燕山大学电子与通信工程系,河北秦皇岛,066004
2. 燕山大学教务处,河北秦皇岛,066004 |
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| 摘 要： | 对VLSI电路中RLC互连线的时延进行了研究,使用改进的一阶模型来近似分布式均匀传输线的传输函数,计算出时域下的阶跃响应并得到简洁的时延计算公式.然后将其应用到具体的RLC互连树中计算源节点到漏节点的时延,其驱动器模型由电阻和电容组成,负载为容性负载.实验结果表明,该模型的计算结果与SPICE仿真结果的误差小于10%,计算量也比基于二阶传输函数的算法大为减少,在计算效率和精度两方面得到较好折衷,可以用于考虑时延效应的优化程序中.
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| 关 键 词： | 集成电路 互连线 时延 RLC互连树 驱动器 |
Estimation of interconnect delay based on RLC model |
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| LI Zhao-hui,SUN Yu-nan.Estimation of interconnect delay based on RLC model[J].Computer Engineering and Design,2008,29(20). |
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| Authors: | LI Zhao-hui SUN Yu-nan |
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| Affiliation: | LI Zhao-hui1,SUN Yu-nan2(1.Department of Electronics , Communication,Yanshan University,Qinhuangdao 066004,China,2.Dean's Office,China) |
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| Abstract: | By using an improved modified one-pole model,the system transfer function for distributed uniform lines up to the first moment is approximated.Then the step response in time domain and a simple delay formula are both calculated.The formula is also applied in the estimation of source-sink delays in an interconnect tree.The model has a driver,which comprises a resistance and capa-citance,and a capacitive load.The results shown that the delay estimates based on the model presented are within 10% of the SPICE c... |
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| Keywords: | IC interconnect delay RLC interconnect tree driver |
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