| 一种基于FPGA的新型快速位同步系统设计 |
| |
| 引用本文： | 唐晓辉,李云,孙智研.一种基于FPGA的新型快速位同步系统设计[J].广西通信技术,2009(2):34-36. |
| |
| 作者姓名： | 唐晓辉 李云 孙智研 |
| |
| 作者单位： | 桂林航天工业高等专科学校,广西桂林,541004 |
| |
| 摘 要： | 提出了一种简单快速的多速率位同步FPGA实现方法，该方法采用码元的上升沿或者下降沿作为触发信号对分频器进行复位来获取码元的位时钟信息。仿真及实验表明：该系统具有较快的位同步建立时间，系统工作稳定、可靠。
|
| 关 键 词： | 位同步 分频器 现场可编程门阵列 |
A New Fast Bit Synchronization System Design Based on FPGA |
| |
| TANG Xiao-hui,LI Yun,SUN Zhi-yan.A New Fast Bit Synchronization System Design Based on FPGA[J].Guangxi Communication Technology,2009(2):34-36. |
| |
| Authors: | TANG Xiao-hui LI Yun SUN Zhi-yan |
| |
| Affiliation: | (Guilin College Of Aerospace Technology, Guangxi Guilin 541004, China) |
| |
| Abstract: | A simple and rapid multi - bit rate simultaneous FPOA implementation, the method used symbol of the rising edge or falling edge as a trigger signal on the Frequency divider to reset for access to the symbol-clock information. And the simulation experiments show that the system has a bit faster set-up time synchronization, system stable and reliable. |
| |
| Keywords: | Bit Synchronization Frequency Divider FPGA |
| 本文献已被 维普 万方数据 等数据库收录！ |
