High-performance devices for a 0.15-μm CMOS technology |
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| Authors: | Shahidi G.G. Warnock J. Fischer S. McFarland P.A. Acovic A. Subbanna S. Ganin E. Crabbe E. Comfort J. Sun J.Y.-C. Ning T.H. Davari B. |
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| Affiliation: | IBM Thomas J. Watson Res. Center, Yorktown Heights, NY; |
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| Abstract: | Devices have been designed and fabricated in a CMOS technology with a nominal channel length of 0.15 μm and minimum channel length below 0.1 μm. In order to minimize short-channel effects (SCEs) down to channel lengths below 0.1 μm, highly nonuniform channel dopings (obtained by indium and antimony channel implants) and shallow source-drain extensions/halo (by In and Sb preamorphization and low-energy As and BF2 implant were used. Maximum high V DS threshold rolloff was 250 mV at effective channel length of 0.06 μm. For the minimum channel length of 0.1 μm, the loaded (FI=FO=3, C=240 fF) and unloaded delays were 150 and 25 ps, respectively |
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