Bringing NoCs to 65 nm |
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Authors: | Pullini A Angiolini F Murali S Atienza D De Micheli G Benini L |
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Affiliation: | Politecnico di Torino, Turin; |
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Abstract: | Very deep submicron process technologies are ideal application fields for NoCs, which offer a promising solution to the scalability problem. This article sheds light on the benefits and challenges of NoC-based interconnect design in nanometer CMOS. The experimental results from fully working 65-nm NoC designs and a detailed scalability analysis are presented. The network on chip (NoC) is a promising solution to the scalability problem. NoCs build upon improvements in bus architecture-for example, in terms of topology design. |
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