低功耗便携式数字音频广播收音机中AAC LC解码器的设计优化

针对目前数字音频广播(DAB)收音机中DSP软件AAC+解码器功耗大的问题，该文提出了低功耗AAC LC解码器的ASIC设计，以极低的硬件代价完成了最基本的DAB+节目解码，加入DAB解码芯片后巧妙地实现了DAB+和DAB两种不同标准的兼容。该文设计优化了反量化与IMDCT算法，使用了分时工作法，从而实现了低功耗。该设计的系统时钟为16.384 MHz，采用0.18 m CMOS工艺，功耗约为6.5 mW，并与DAB信道解码结合，通过了FPGA开发板上的实时验证，且完成了芯片的版图设计，芯片面积为14 mm2。

AAC LC Decoder Design Optimization for Low-power Portable DAB Radio

In view of high power consumption of current Digital Audio Broadcasting (DAB) radios AAC+ decoder implemented in DSP processor, this paper proposes an ASIC design of low-power AAC LC decoder. The design achieves the most basic decoding DAB+ program with very low hardware cost, and realizes skillfully the compatibility of two different standards DAB+ and DAB after adding to the DAB decoder chip. In order to achieve low power consumption, this design optimizes the inverse quantization and IMDCT algorithm and uses the time-sharing method. The system clock runs at 16.384 MHz, adopts 0.18 m CMOS technology, and power consumption is about 6.5 mW. Combined with the DAB channel decoder, it passes the real-time verification on the FPGA development board and completes the chip layout, and the chip area is 14 mm2.