一种新型Sigma-Delta调制器结构的研究

本文提出一种新颖的∑-△调制器结构设计，实现用较低比特位数的数字信号表示较高比特位数的高速信号。与传统的∑-△调制器不同，该调制器采用了新颖的量化噪声整形滤波器使输出信号具有较低比特位数。在调制器的结构设计中，采用了流水线一反馈型的实现结构，使处理过程消除了乘法运算。该结构易于系统实现和提高处理速度。本文用Simulink对调制器进行了仿真研究。研究结果表明本文提出的调制器适合于高速信号的实时处理。

A Novel Sigma-Delta and Its Architecture Design

A novel sigma-delta modulator is presented to denote the signals with lower bits. The most eminent feature of the proposed modulator is the use of novel noisy shaping filter to perform output at lower bits. A pipeline-feedback architecture is designed intentionally to remove multipliers. This architecture is easy to implement and can be used to speed up signal processing. Simulations with Simulink indicate that the proposed modulator is suitable for the real-time signal processing.