基于FPGA的简易MCU设计

以FPGA作为实验验证平台,独立地设计能够执行相应指令的MCU内核,整个系统的核心是一个由系统时钟驱动的全局状态机,他控制着所有指令的执行时序。系统内部几乎所有的寄存器都直接与8位的数据总线相连,这种结构使得数据从一个寄存器传输到另一个寄存器只需一个时钟周期,同传统的51核相比减少了传输类指令的时钟周期。加减乘除由不同的逻辑模块完成,这些逻辑模块通过一个交叉阵列开关连接至总线,由指令译码器直接控制交叉开关的连接。测试结果表明在指令的译码以及执行的过程中,各个寄存器和相应总线的数据均符合设计要求。

Simple MCU Design Based on FPGA

This paper designs a system of MCU on which some instructions can be operated.The core of the system is a status machine driven by clock.Almost all of the inner registers connect through a data bus and the behavior that data transfers from one register to another can be completed in one period cycle.Adding,subtraction,multiplication and division have its own logic cell.These logic cells have been connected to data bus through a across array of switch.They are controlled by instruction decoder.Finally,the results indicate the values of data bus and corresponding registers meet the desire of design.