| 不断推进的圆片级三维封装 |
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| 引用本文： | Philip Garrou,高仰月.不断推进的圆片级三维封装[J].电子工业专用设备,2006,35(12):19-21. |
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| 作者姓名： | Philip Garrou 高仰月 |
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| 作者单位： | IEEE Fellow IEEE CPMT Society Program Consultant，TRI International，Research Triangle，IEEE Fellow IEEE CPMT Society，Program Consultant，TRI International，Research Triangle |
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| 摘 要： | 当减小芯片面积时,3-D封装能减轻互相连接所带来的延迟问题,根据集成电路是否已经进行了3-D互相的设计,描述了3种选择方法。
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| 关 键 词： | 三维封装 系统级封装 垂直互联 通孔 |
| 文章编号： | 1004-4507(2006)12-0019-03 |
| 收稿时间： | 11 5 2006 12:00AM |
| 修稿时间： | 2006年11月5日 |
Wafer-Level 3-D integration moving forward |
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| Philip Garrou.Wafer-Level 3-D integration moving forward[J].Equipment for Electronic Products Marufacturing,2006,35(12):19-21. |
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| Authors: | Philip Garrou |
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| Affiliation: | IEEE Fellow, IEEE CPMT Society, Program Consultant, TRI International, Research Triangle;IEEE Fellow, IEEE CPMT Society, Program Consultant, TRI International, Research Triangle |
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| Abstract: | 3-D integration can alleviate interconnect delay problems, while reducing chip area. Three options are described, based on whether the ICs have been designed for 3-D interconnection. |
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| Keywords: | 3-D integration SIP Vertical interconnection Through-Via |
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