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| VLSI随机工艺变化下互连线建模与延迟分析 | |
| 引用本文： | 张瑛,王志功,Janet M. Wang. VLSI随机工艺变化下互连线建模与延迟分析[J]. 电路与系统学报, 2009, 14(5) |
| 作者姓名： | 张瑛 王志功 Janet M. Wang |
| 作者单位： | 1. 东南大学,射频与光电集成电路研究所,江苏,南京,210096;南京邮电大学,电子科学与工程学院,江苏,南京,210046 2. 东南大学,射频与光电集成电路研究所,江苏,南京,210096 3. 亚利桑那大学,电子工程系,美国亚利桑那州 AZ8742 |
| 摘 要： | 目前互连线的工艺变化问题已成为影响超大规模集成电路性能的重要因素.考虑了互连线工艺变化的空间相关性,将工艺参数变化建模为具有自相关性的随机过程,采用数值仿真及拟合方法得到寄生参数的近似表达式,最后基于Elmore延迟度量分析了随机工艺变化对互连延迟的影响,提出了工艺变化下互连延迟统计特性的估算方法,并通过仿真实验对方法的有效性进行了验证. |
| 关 键 词： | 工艺变化 空间相关性 互连线 Elmore延迟 蒙特卡洛法 |
Modeling of interconnects and delay analysis in the presence of Random VLSI process variations |
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| ZHANG Ying,WANG Zhi-gong,Janet M. Wang. Modeling of interconnects and delay analysis in the presence of Random VLSI process variations[J]. Journal of Circuits and Systems, 2009, 14(5) | |
| Authors: | ZHANG Ying WANG Zhi-gong Janet M. Wang |
| Affiliation: | ZHANG Ying1,2,WANG Zhi-gong1,Janet M.Wang3(1.Institute of RF&OE-ICs of Southeast University,Nanjing 210096,China,2.College of Electronics Science , Engineering,Nanjing University of Posts , Telecommunications,Nanjing 210046,3.Department of Electrical , Computer Engineering,College of Engineering , Mines,The University of Arizona,Arizona AZ8742,USA) |
| Abstract: | Interconnect process variations have become an important factor which affects the performance of very large scale integrated circuits.Considering the spatial correlation of interconnect process variations,they are modeled as stochastic processes with self-correlations.The approximate expressions of paracitic parameters are obtained by numerical simulations and fitting method.Finally,on the basis of Elmore delay metric the impact of random processes variations on interconnect delay is analyzed,and the method... |
| Keywords: | process variations spatial correlation interconnects Elmore delay Monte Carlo method |
| 本文献已被 CNKI 万方数据 等数据库收录！ | |