工艺变化条件下互连延时最小缓冲器插入方法

提出了一种考虑工艺变化下快速时序优化的缓冲器插入方法，该方法在布线区域内对线网结构进行图变换，把随机问题变为确定性问题，也就是把工艺变化下缓冲器插入时序优化问题等效成统计最短路径问题；同时，在构建图的过程中提出一种有效节点存储算法，将有效节点个数从指数级降为平方级，大大提高了存储和运行的效率. 针对90 nm、65 nm和45 nm工艺下全局互连线缓冲器插入对本方法进行分析和验证，插入结果与已有方法的结果一致，证明了本方法的有效性；将该方法应用于直线线网和树型线网这两类集成电路中实际的互连线网，在分别插入17个缓冲器和3个缓冲器下达到了最优时序优化结果.

Buffer Insertion Method under Process Variations for Delay Minimization

A buffer insertion method of a rapid timing optimization under process variation is proposed. The method carries out graph transformation on wire net in routing area, and so the random problem becomes a deterministic problem i.e. the buffer insertion problem for reducing time delay will be equivalent to statistics the shortest path problem. Moreover, we propose a valid node storage algorithm, which is optimized in constructing the graph process, and is greatly improving the memory space and working efficiency. In experiment section, the method is firstly used in 90 nm, 65 nm and 45 nm process global interconnect buffer insertion and analysis, and the insertion results are consistent with reference result, which confirms the validity of this method. Meanwhile, the algorithm was applied to two kinds of actual interconnect nets in integrated circuit: simple wire net and tree type wire net, which gets perfect timing optimization results based 17 inserted buffers and 3 inserted buffers respectively.