A 1.8-V 256-Mb Multilevel Cell NOR Flash Memory With BGO Function

This paper describes a 1.8-V-only 256-Mb four-level-cell (2 b/cell) NOR flash memory with background operation (BGO) function fabricated in a 130-nm CMOS self-aligned shallow trench isolation (SA-STI) process technology. The new memory array architecture is adopted in which the flash source is connected by local interconnect to reduce the source resistance and constrain the floating-gate coupling effect. The mirrored current sensing read architecture for multilevel-cell operation at a supply voltage of 1.8 V has realized a fast asynchronous random access time (67 ns) and burst read at 54 MHz. A high speed and high reliability of program/erase cycling (100 k) has been achieved by dual-step pulse program algorithm and optimized erase sequence. Page program time and block erase time are 1.54 ms/2 kb and 538 ms/1 Mb, respectively