基于扫描链平衡的3D SoC测试优化方法

三维芯片由于其高性能和低功耗越来越受到人们的欢迎。SoC技术是把一个完整的系统集成到单个(或少数几个)芯片上,从而实现整个系统功能复杂的集成电路。以细粒度划分的3D SoC实现了真正意义上的3D芯核。它降低了单个芯核内的局部和全局互连线的长度,在功耗和性能方面会有很大的改进。但是随着划分层数的不同,测试开销也会发生变化。本文通过扫描链平衡提出考虑测试时间和测试存储的测试开销函数,以便找到最优的划分层数。在ITC’02基准SoC集上的实验结果表明,通过扫描链平衡技术后得到的测试开销比普通测试开销最高降低了19.9%。

3D SoC test optimization method based on balance of scan chain

Three-dimensional （3D） chip become more and more popular because of its high performance and low power consumption. System on Chip （SoC） technology integrates complete system into a single （or few） chip. The 3D SoC based on fine-granularity partitioning is the true 3D chip. It reduces the local and global interconnects, and has great improvement in power consumption and performance. But with the difference of tiers partitioned, the test cost can be dif- ferent. A test cost function considering the test time and test capacity in order to find the optimal partitioning tiers based on the balance of scan chain is proposed in this paper. The experimental results on ITC＇02 SoC benchmarks reveal that the test cost based on balance of scan chain can reduce 19.9% mostly compared with the common test cost.