一种动态功能重构SRAM的设计与实现

SRAM作为常用的存储器,在速度和功耗方面有一定的优势,但其较大的面积是影响成本的主要原因。文章设计了一种256×8位动态功能重构的SRAM模块,在完成基本SRAM存储功能的前提下,通过设置重构标志信号tag及附加的控制逻辑信号,复用基本SRAM模块存储资源,使系统完成FIFO的顺序存储功能。整个设计一方面拓展了基本存储体的功能,另一方面,FPGA验证结果显示：实施重构方案后同一块FPGA器件的硬件资源利用率明显提高了。最后,采用插入门控时钟的低功耗优化方案进行了DC综合,结果显示动态功耗降低了59．6％。经过“重构”的方式后,只增加了少量电路便可以实现动态数字电路的基本功能,一方面完成了功能上的拓展,另一方面提高了存储模块硬件资源的利用率,使SRAM具有了更高的性价比。

Design and Implementation of a Dynamic Reconfigurable SRAM

As one of commonly used memories,SRAM dominates in the speed and power consumption, and is inferior in area cost.In this paper,a 256×8 bit dynamic function reconfigurable SRAM module was designed.At the implementation of the basic storage function precondition,the system can accomplish the FIFO utilizing the SRAM resources,by setting a reconfigurable signal tag and additional control signals.This design not only extended the function of basic memory module, but also enhanced the efficiency of hardware resources to the same FPGA chip after reconfiguration.Finally, DC synthesis was obtained by inserting clock-gating low-power optimization,the result showed that the total dynamic power was reduced by 59.6%. After "reconfiguration",the memory system can not only realize the extended function by utilizing a few circuits which can fulfill the basic function of dynamic digital circuits,but also enhance the use efficiency of hardware resources in memory modules. Obviously,cost performance of the SRAM is improved.