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Implementation and Investigation of an Optimal Full Adder Design for Low Power and Reduced Delay Conditions |
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| Authors: | Praghash K. Arun Metha S. Sai Tanuja B. Preethi K. Chandana N. P. N. S. |
| Affiliation: | 1.Department of Electronics and Communication Engineering, Koneru Lakshmaiah Education Foundation, Vaddeswaram, AP, India ;2. Department of Electronics and Communication Engineering, Christ University, Bengaluru, Karnataka, India ; |
| Abstract: | Wireless Personal Communications - Full adder is one of the important components in electronics, used for various fundamental processing algorithms such as addition and multiplication. The... |
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