A video DSP with a macroblock-level-pipeline and a SIMD typevector-pipeline architecture for MPEG2 CODEC |
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| Authors: | Toyokura M Kodama H Miyagoshi E Okamoto K Gion M Minemaru T Ohtani A Araki T Takeno H Akiyama T Wilson B Aono K |
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| Affiliation: | Semicond. Res. Center, Matsushita Electr. Ind. Co. Ltd., Osaka; |
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| Abstract: | A video DSP with macroblock-level-pipeline and a SIMD type vector-pipeline architecture (VDSP2) has been developed, using 0.5 μm triple-layer-metal CMOS technology. This 17.00 mm×15.00 mm chip consists of 2.5 M transistors, and operates at 100 MHz. The real-time encoder and decoder specified in the MPEG2 main profile at the main level can be realized with two VDSP2's and a motion estimation (ME) unit, and one VDSP2 respectively, at an 80 MHz clock rate, with a total power dissipation of 4.2 W at 3.3 V |
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