Interfacial delamination and fatigue life estimation of 3D solder bumps in flip-chip packages

Detailed three-dimensional finite element analysis was carried out for area-array solder-bumped flip-chip packages. The analysis enabled determinations of accurate three-dimensional effects on stress distributions as well as local fracture behaviors under thermal load. The 3D analysis also estimated thermal fatigue life of solder bumps. Since dimensions of various components span more than three orders of magnitude, the multi-scale finite element models were utilized to elucidate detailed deformation state near solder bumps. The global–local approach identified of critical solder bumps due to the overall deformation and investigated of interfacial delamination at microstructural level. The local model contained a single solder bump and sub-micron UBM layers. The two-step modeling approach enabled accurate fracture analysis otherwise difficult in large 3D models. Our analysis found the crack driving force and preferred delamination direction based on the 3D J-integral calculations. Shear deformations within and surrounding solder bump connectors were also investigated. The results revealed higher deformation in the 3D model than those predicted from 2D models. Additionally, the strain components were different. This has an important implication on the plastic flow characteristics during cyclic loading. Our model estimated about 25% greater steady-state shear strains in the 3D model than those in the 2D models. This result suggests a much shorter fatigue life than that based on the 2D analysis.