| 一种CMOS微电子测试图形的设计 |
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| 引用本文： | 彭力.一种CMOS微电子测试图形的设计[J].微电子学,1992,22(3):49-54. |
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| 作者姓名： | 彭力 |
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| 作者单位： | 华晶公司中央研究所 前24所分所，无锡 214035 |
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| 摘 要： | 本文介绍一种CMOS集成电路微电子测试图形——E2-PED,它是针对CMOS EEPR-OM电路的研制而设计的,也可以用于一般的CMOS电路工艺:文章描述了E2-PED所含有的各种微电子测试结构以及设计布图,给出了这些结构的构成及其作用。
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| 关 键 词： | 集成电路 微电子 测试 图形 CMOS |
The Design of A CMOS IC Test Pattern |
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| Peng Li Central Institute,Huajins Electronics Group Corp. Wuxi,Jiangsu.The Design of A CMOS IC Test Pattern[J].Microelectronics,1992,22(3):49-54. |
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| Authors: | Peng Li Central Institute Huajins Electronics Group Corp Wuxi Jiangsu |
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| Affiliation: | Peng Li Central Institute,Huajins Electronics Group Corp. Wuxi,Jiangsu,214035 |
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| Abstract: | A microelectronic test pattern for CMOS ICs, E2-PED, is introduced in the paper. It is designed for the development of CMOS EEPROM and it may be applied to conventional processes for CM32 devices. Different microelectonic test structures contained in EL-PED and the design layout are described. The makeup of these structures and their functions are also provided. |
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| Keywords: | CMOS IC Microelectronic test pattern EEPROM |
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