High performance hardware architecture for singular spectrum analysis of Hankel tensors |
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| Affiliation: | 1. Department of Electronic Engineering, City University of Hong Kong, Hong Kong;2. Department of Applied Mathematics, Hong Kong Polytechnic University, Hong Kong;1. Indian Institute of Technology Guwahati, Assam, India;2. Indian Institute of Technology Bhiali, India;1. Faculty of Engineering and Physical Sciences, Department of Computer Science, University of Surrey, Guildford, GU2 7XH, UK;2. Evolution and Genomic Sciences, School of Biological Sciences, Faculty of Biology, Medicine and Health, The University of Manchester, Manchester, M13 9PT, UK;1. Department of Pathology, Shanghai Medical College, Fudan University, Shanghai 200032, China;2. Department of Pathology, Huashan Hospital, Fudan University, Shanghai 200040, China;1. Riphah International University Islamabad, Pakistan;2. UCERD, Islamabad, Pakistan;3. LAAS-CNRS, Université de Toulouse, CNRS, INPT, Toulouse, France |
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| Abstract: | This paper presents a hardware architecture for singular spectrum analysis of Hankel tensors, including computation of tucker decomposition, tensor reconstruction and final Hankelization. In the proposed design, we explore two level of optimization. First, in algorithm level, we optimize the calculation process by exploiting the Hankel property to reduce the computation complexity and on-chip BRAM resource usage. Secondly, in hardware level, parallelism is explored for acceleration. Resource sharing is applied to reduce look-up tables (LUTs) usage. To enable flexibility, the number of processing elements (PEs) can be changed through parameter setting. Our proposed design is implemented on Field-Programmable Gate Arrays (FPGAs) to process third order tensors. Experiment results show that our design achieve a speed-up from 172 to 1004 compared with CPU implementation via Intel MKL and 5 to 40 compared with GPU implementation. |
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