| 高速数据采集系统中的FPGA的设计 |
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| 引用本文： | 马秀娟, 牛进鹏, 考丽, 赵国良,. 高速数据采集系统中的FPGA的设计[J]. 电子器件, 2007, 30(4): 1372-1374,1379 |
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| 作者姓名： | 马秀娟 牛进鹏 考丽 赵国良 |
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| 作者单位： | 哈尔滨工程大学,哈尔滨,150001;哈尔滨工业大学,山东,威海,264209;哈尔滨工业大学,山东,威海,264209;哈尔滨工程大学,哈尔滨,150001 |
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| 摘 要： | 提出了利用FPGA技术把缓存FIFO、锁存电路、时序电路、控制电路等分散的电路模块集中起来作为独立的缓存及控制电路,实现了数据的高速缓存,防止了数据丢失;产生了严格的时序逻辑,保证了系统的可靠性.利用乒乓锁存降低了对缓存速度的要求并将数据合并成32位,易于与DSP数据传输.电路模块简单可靠,易于系统调试.详细介绍了FPGA的电路模块的设计.
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| 关 键 词： | 高速数据采集 FPGA 乒乓锁存 |
| 文章编号： | 1005-9490（2007）04-1372-03 |
| 修稿时间： | 2006-07-13 |
Design of FPGA in the High-Speed Data Acquisition |
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| MA Xiu-juan,NIU Jin-peng,KAO Li,ZHAO Guo-liang. Design of FPGA in the High-Speed Data Acquisition[J]. Journal of Electron Devices, 2007, 30(4): 1372-1374,1379 |
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| Authors: | MA Xiu-juan NIU Jin-peng KAO Li ZHAO Guo-liang |
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| Affiliation: | 1. Harbin Engineering University, Harbin 150001, China; 2. Harbin Institute of Technology, Weihai Shandong 264209, China |
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| Abstract: | The FPGA concentrates the buffer FIFO, the timing circuit, the control circuit and dispersive component into an independent circuit block, which can not only relize high-speed buffer to avoid losing data, but also give birth to the strict timing logic to insure the reliability of the system. The buffer velocity is fell by using PingPong latch which combine data into 32 bits being easy to connect with DSP. The circuit is simple , reliable and easy to debug the system. The design of FPGA in the system is presented in detail. |
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| Keywords: | high speed data acquisition FPGA PingPong latch |
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