| 非理想逻辑输入对IBIS仿真的影响及改进方法 |
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| 引用本文： | 王骝.非理想逻辑输入对IBIS仿真的影响及改进方法[J].微电子学与计算机,2008,25(6). |
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| 作者姓名： | 王骝 |
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| 作者单位： | 上海交通大学,微电子学院,上海,200240 |
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| 摘 要： | 在高速数字电路端口建模标准IBIS的基础上,提出一种改进仿真电路结构和算法的方法,用于处理经由传输线传输的非理想信号影响IBIS驱动器仿真精度问题.简述了IBIS瞬态提取采的四波形算法,在IBIS驱动器模型中引入了表征输入影响的调制参数K,分析和比较了改进的模型与晶体管模型、B参数模型的仿真结果,以说明改进后精度的提高.
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| 关 键 词： | 输入输出电路模型 行为级建模 时序仿真 |
The Effect of Non-ideal Input on IBIS Simulation and Improvement |
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| WANG Liu.The Effect of Non-ideal Input on IBIS Simulation and Improvement[J].Microelectronics & Computer,2008,25(6). |
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| Authors: | WANG Liu |
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| Abstract: | A new method for improving IBIS simulation with slope input is proposed.It resolves the problem that IBIS driver model is affected by the signal with delays.A 4 waveform algorithm is described in this paper and parameter K is used for simulating the affect of input slope.The new macro-circuit works with HSPICE and produces a better simulation result considering the input effect compared with B-element and the original transistor model. |
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| Keywords: | IBIS behavior model timing analysis |
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