高码率LDPC码译码器的优化设计与实现

本文以CCSDS推荐的7/8码率LDPC码为例，提出了一种适于高码率LDPC码译码器的硬件结构优化方法。高码率的LDPC码通常也伴随着行重与列重的比例较高的问题。本方法是在拆分校验矩阵的基础上，优化常用的部分并行译码结构，降低了高码率LDPC码译码时存在的校验节点运算单元(CNU)与变量节点运算单元(VNU)之间的复杂度不平衡，并由此提高了译码器的时钟性能。实验证明，本文方案提供的结构与常用的部分并行译码结构相比，节省硬件资源为41％；采用与本文方案相同的硬件资源而未经矩阵拆分的部分并行译码方案的码速率为本文方案的75％。

Optimized Decoder Design and Implement for High Rate LDPC Codes

This paper brings up with a hardware structure optimized method which is suitable for high code rate LDPC decoder, for example, CCSDS recommended LDPC (Low-Density Parity-Check code) code with ?code rate of 7/8. LDPC code with high code rate is usually concomitant with problem that row weight is far larger than the column weight. This optimized method is based on check matrix splitting, it also optimizes the common components of parallel decoder structure, and reduces complexity imbalance between Check Node processing Units (CNUs) and Variable Node processing Units (VNUs) existed in high code rate LDPC decoder. Thus, clock performance of the decoder is improved. Experiment has proved, compared with usual partial parallel decode structure, structure provided by this paper saves 41% hardware resources, and the code rate of partial parallel decode structure which adopts the same amount of hardware resources is just 75% than code rate of the structure in this paper.