Statistical modeling of reliability in logic devices

Due to continuous technology scaling VLSI circuits feature an increasing susceptibility to transient faults. While complete elimination of errors cannot be guaranteed, current mitigation techniques based on circuit improvement or architectural measures cause a large overhead in terms of area and energy consumption. A more efficient possibility to cope with transient faults can be to tolerate hardware errors at low physical levels and handle them at higher system levels. This can be achieved by reusing error handling capabilities – such as channel decoders – or introducing specialized error correction blocks that take advantage of the system characteristics by concentrating the effort on the components and bits most crucial for system operation. To enable this approach the influence of hardware errors on system performance needs to be evaluated, requiring spatial and temporal models of error propagation in the system. Since Monte Carlo simulation of complex systems is not feasible, a statistical modeling technique of logic gates and circuits is introduced. This approach allows modeling of noise and variability influences on logic gates as well as correlation due to reconvergent fan-out with an error of 5% compared to Monte Carlo simulation but with considerably less runtime.