A 6-ns 4-Mb CMOS SRAM with offset-voltage-insensitive current senseamplifiers |
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| Authors: | Ishibashi K Takasugi K Komiyaji K Toyoshima H Yamanaka T Fukami A Hashimoto N Ohki N Shimizu A Hashimoto T Nagano T Nishida T |
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| Affiliation: | Central Res. Lab., Hitachi Ltd., Tokyo; |
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| Abstract: | A 4-Mb CMOS SRAM with 3.84 μm2 TFT load cells is fabricated using 0.25-μm CMOS technology and achieves an address access time of 6 ns at a supply voltage of 2.7 V. The use of a current sense amplifier that is insensitive to its offset voltage enables the fast access time. A boosted cell array architecture allows low voltage operation of fast SRAM's using TFT load cells |
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