| 一种二极管桥结构7位60 MSPS采样保持器 |
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| 引用本文： | 孟晓胜,王百鸣,潘志铭. 一种二极管桥结构7位60 MSPS采样保持器[J]. 微电子学, 2007, 37(4): 570-573 |
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| 作者姓名： | 孟晓胜 王百鸣 潘志铭 |
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| 作者单位： | 1. 深圳大学,光电子学研究所,广东,深圳,518060
2. 深圳大学,信息工程学院,EDA技术中心,广东,深圳,518060 |
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| 基金项目： | 国家自然科学基金;广东省深圳市科技计划 |
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| 摘 要： | 提出了一种二极管桥结构的采样保持器。理论分析和实验仿真结果表明，该采样保持器采样率达60MSPS，在0．6～5．0MHz输入信号频率范围内，其有效位数达到7．43～6．68位。利用这种二极管桥结构的电压差异，可以降低保持电容上的电压跌落率，提高精度和采样率。
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| 关 键 词： | 采样保持器 二极管桥结构 采样率 有效位数 总谐波失真 |
| 文章编号： | 1004-3365（2007）04-0570-04 |
| 修稿时间： | 2006-11-27 |
7-Bit 60 MSPS Sample-and-Hold Circuit with Diode Bridge Architecture |
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| MENG Xiao-sheng,WANG Bai-ming,PAN Zhi-ming. 7-Bit 60 MSPS Sample-and-Hold Circuit with Diode Bridge Architecture[J]. Microelectronics, 2007, 37(4): 570-573 |
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| Authors: | MENG Xiao-sheng WANG Bai-ming PAN Zhi-ming |
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| Affiliation: | 1. Institute of Optoelectronics, Shenzhen University, Shenzhen, Guangdong 518060, P. R. China;2. The EDA Technology Center, Collegeof Inform. Engineer. , Shenzhen University, Shenzhen, Guangdong 518060, P. R. China |
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| Abstract: | A new sample-and-hold circuit based on diode bridge architecture was designed. Results from both theoretical analysis and experimental simulation show that the proposed S/H circuit has a sampling rate of 60 MHz with ENOB at 7. 43-6.68 bits for 0. 6-5.0 MHz sine signal input. In the proposed S/H amplifier, voltage drop-rate on hold capacitor can be reduced, and both sampling rate and accuracy can be improved by making use of voltage difference between diode bridges. |
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| Keywords: | Sample-and-hold amplifier Diode bridge architecture Sampling rate ENOB Total harmonic distortion |
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