Data Buffering and Allocation in Mapping Generalized Template Matching on Reconfigurable Systems

Image processing algorithms for 2D digital filtering, morphologic operations, motion estimation, and template matching involve massively parallel computations that can benefit from using reconfigurable systems with massive field programmable gate array (FPGA) hardware resources. In addition, each algorithm can be considered a special case of a generalized template matching (GTM) operation. Application performance on reconfigurable computer systems is often limited by the bandwidth to host or off chip memory. This paper describes the GTM operation and characterizes the data allocation and buffering strategies for the GTM operation on reconfigurable computers. Several mechanisms that support different levels of parallelism are proposed and summarized in the paper. Finally, the implementation of an infrared automatic target recognition application on two commercial FPGA boards is used to demonstrate the various design options with different data allocation and buffering mechanisms and the pruning of the design space based on the FPGA area and memory constraints.