Device-physics-based analytical model for SET pulse in sub-100 nm bulk CMOS Process

Through revising the process of charge collection for reversed drain-bulk junction,a bias-dependent SPICE model is proposed which includes the bipolar amplification effect that cannot be ignored in PMOS.The model can capture the plateau effect,and produce current and voltage pulse shapes and widths that are consistent with TCAD simulation.Considering the case of connecting load,it is still valid.For combination and sequential logic circuits,the SET pulsewidths and LET upset threshold from SPICE model are consistent with TCAD simulations.