A 120-MHz BiCMOS superscalar RISC processor |
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| Authors: | Tanaka S. Hotta T. Murabayashi F. Yamada H. Yoshida S. Shimamura K. Katsura K. Bandoh T. Ikeda K. Matsubara K. Saitou K. Nakano T. Shimizu T. Satomura R. |
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| Affiliation: | Res. Lab., Hitachi Ltd., Ibaraki; |
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| Abstract: | A superscalar RISC processor contains 2.8 million transistors in a die size of 16.2 mm×16.5 mm, and utilizes 3.3 V/0.5 μm BiCMOS technology. In order to take advantage of superscalar performance without incurring penalties from a slower clock or a longer pipeline, a tag bit is implemented in the instruction cache to indicate dependency between two instructions. A performance gain of up to 37% is obtained with only a 3.5% area overhead from our superscalar design |
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