| 基于FPGA的数字视频异步帧频转换器设计 |
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| 引用本文： | 冯永茂,徐秀知,王骞,丁铁夫.基于FPGA的数字视频异步帧频转换器设计[J].电子器件,2007,30(3):1064-1067. |
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| 作者姓名： | 冯永茂 徐秀知 王骞 丁铁夫 |
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| 作者单位： | 1. 中国科学院长春光学精密机械与物理研究所,长春,130033;中国科学院研究生院,北京,100039
2. 中国科学院长春光学精密机械与物理研究所,长春,130033 |
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| 摘 要： | 利用DVI接口的同步控制信号生成内存写入地址,帧频触发信号控制内存读取地址的设计思想,在FPGA中实现了从任意帧频的数字视频源转换到50 Hz或60 Hz帧频.给出了帧频转换器的基本硬件结构,和实用的设计方法,并讨论了数据缓冲区设置深度与内存操作带宽的关系.
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| 关 键 词： | 数字视频接口 帧频合成 FPGA 缓冲区管理 |
| 文章编号： | 1005-9490（2007）03-1064-04 |
| 修稿时间： | 2006-07-14 |
Digital Video Asynchronous Frame Rate Converter Design Based on FPGA |
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| FENG Yong-mao,XU Xiu-zhi,WANG Qian,DING Tie-fu.Digital Video Asynchronous Frame Rate Converter Design Based on FPGA[J].Journal of Electron Devices,2007,30(3):1064-1067. |
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| Authors: | FENG Yong-mao XU Xiu-zhi WANG Qian DING Tie-fu |
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| Affiliation: | 1. Changchun Institute of Optics, Fine Mechanics and Physics, Chinese Academy of Sciences, Changchun 130033, China ;2.Graduate School of the Chinese Academy of Sciences, Beijing 100039, China |
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| Abstract: | The main goal of this paper is to introduce a method on how to realize the digital video asynchronous frame rate converter in a FPGA chip. The DVI port of PC is one common way to get the digital video signal. The DVI scan synchronous signal such as Vsync, DE and Pixel clock are used to generate the write addresses of its Pixel data, and the frame rate synchronous pulse is generated to synchronize the video Synthesizer, cache management units, memory controller and all other logic modules in the FPGA chip. Not only the 50 Hz or 60 Hz frame rate can be realize, through this simple but useful method, any frame rate can be converted which are limited by the memory data bandwidth. A dual channel with spread word length memory architecture and the cache depth setting skills are also introduced in this paper. |
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| Keywords: | digital visual interface frame rate converter FPGA cache management |
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