基于增强型延时感知CSE算法的AES S盒电路优化设计

针对高级加密标准（AES）S-盒优化，提出了一种增强型延时感知公共项消除（CSE）算法.该算法能够在不同延时约束条件下优化多常数乘法运算电路，并给出从最小延时到最小面积全范围的面积-延时设计折中.采用该算法优化了基于冗余有限域算术的S盒实现电路，确定了延时最优、面积最优的两种S盒构造.实例优化结果表明所提出算法的优化效率高、优化结果整体延时小.所设计的S盒电路基于65nm CMOS工艺库综合，结果表明，对比于已有文献中S盒复合域实现电路，所提出面积最优S盒电路的面积-延时积最小，比目前最小面积与最短延时的S盒组合逻辑分别减少了17.58%和19.74%.

Construction of Optimum Circuit for AES S-Box Based on an Enhanced Delay-Aware Common Subexpression Elimination Algorithm

Aiming at the optimization of advanced encryption standard (AES) S-box,an enhanced delay-aware common subexpression elimination algorithm is proposed.Under different delay constraints,the proposed algorithm can not only optimize multiple constant multiplication circuit,but also provide all of the design trade-offs,from the shortest feasible delay to the smallest area.Two constructions of S-box based on redundant finite field arithmetic which have optimal delay or the optimal area are derived using the algorithm.The results obtained through optimizing examples show the algorithm achieves high optimization efficiency and better overall delay optimization effect.In 65nm CMOS technology,the proposed S-box circuit which has the optimal area has the minimum area-delay product among the S-boxes based on composite field architecture.Compared with the smallest S-box and the shortest delay S-box,it saves about 17.58% and 19.74% of the area-delay product respectively.