基于QN旋转布局的10位500 MS/s分段电流舵DAC

针对分段电流舵数/模转换器（Digital-to-Analog Converter,DAC）,通过理论分析和推导,研究电流源阵列系统失配误差和寄生效应对非线性的影响,采用电流源阵列Q^N旋转游走版图布局方案,能够减小电流源系统失配的一次误差,而且版图布线简单,由寄生效应引起的电流源失配较小,利于DAC非线性的优化.基于0.18μm CMOS,采用"6+4"的分段结构,设计了一种10位500MS/s分段电流舵DAC,流片测试结果表明,在输入频率为1.465MHz,采样速率为500MS/s的条件下,无杂散动态范围（Spurious Free Dynamic Range,SFDR）为64.9dB,有效位数（Effective Number of Bits,ENOB）为8.8 bit,微分非线性误差（Differential Non-linearity,DNL）和积分非线性误差（Integral Non-linearity,INL）分别为0.77LSB和1.12LSB.

A 10-bit 500MS/s Current Steering DAC with QN Rotary Layout

According to the segmented current steering digital-to-analog converter (DAC),the influence of current mismatch and parasitics in the current array on the nonlinearity of DAC is discussed by theoretical analysis and derivation.A layout plan for the current array,Q^N rotary walk scheme is utilized for optimizing the nonlinearity of DAC.The metal connection in this layout scheme is relatively simple and the current mismatch caused by parasitic effect is small.With the segmented structure of 6 bit thermometer code and 4 bit binary code,a 10 bit DAC is realized in a 0.18μm CMOS by using the above layout plan.The measurement results show that the differential non-linearity (DNL) and the integral non-linearity (INL) of the DAC with Q^N rotary layout scheme are 0.77 LSB and 1.12 LSB.With 500MS/s sampling rate and 1.465MHz input frequency,the spurious free dynamic range (SFDR) and the effective number of bits (ENOB) are 64.9dB and 8.8bit,respectively.