| 基于0.13微米锗硅BiCMOS工艺的80 Gb/s 2:1 复接器 |
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| 引用本文： | 赵衍,王志功,李伟. 基于0.13微米锗硅BiCMOS工艺的80 Gb/s 2:1 复接器[J]. 半导体学报, 2009, 30(2): 025008-4 |
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| 作者姓名： | 赵衍 王志功 李伟 |
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| 摘 要： | 本文介绍了基于0.13微米锗硅BiCMOS工艺设计的超高速2:1复接器芯片，工艺fT为103 GHz。为了最大限度提高工作速度，系统方案进行了优化，采用了选择器输出直接驱动片外50 Ω负载的形式，并在输入级集成了两个宽带数据放大器和一个时钟放大器。经测试，芯片输出眼图达到了80 Gb/s的速率，单端电压摆幅为160 mV。
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| 关 键 词： | 希尔伯特单元，复接器，选择器，超高速集成电路，宽带放大器。 |
| 收稿时间： | 2008-08-11 |
| 修稿时间： | 2008-09-22 |
80 Gb/s 2:1 multiplexer in 0.13-mm SiGe BiCMOS technology |
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| Zhao Yan,Wang Zhigong and Li Wei. 80 Gb/s 2:1 multiplexer in 0.13-mm SiGe BiCMOS technology[J]. Chinese Journal of Semiconductors, 2009, 30(2): 025008-4 |
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| Authors: | Zhao Yan Wang Zhigong Li Wei |
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| Affiliation: | Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China;Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China;Institute of RF- & OE-ICs, Southeast University, Nanjing 210096, China |
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| Abstract: | This work presents an ultra-high speed 2:1 multiplexer (MUX) in a SiGe BiCMOS technology with fT= 103 GHz. To boost the operating speed, the system scheme is optimized including a 2:1 selector circuit directly driving an external 50 W load, and two wide-band data buffers and one clock buffer in the input stage. The chip exhibited an open eye at 80 Gb/s with a 160 mV single-ended voltage swing. |
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| Keywords: | Gilbert cell multiplexer selector ultrahigh-speed integrate circuit wideband buffer |
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