A second-order semidigital clock recovery circuit based on injection locking |
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Authors: | Hiok-Tiaq Ng Farjad-Rad R Lee M-JE Dally WJ Greer T Poulton J Edmondson JH Rathi R Senthinathan R |
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Affiliation: | Velio Commun. Inc., Milpitas, CA, USA; |
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Abstract: | A compact (1 mm /spl times/ 160 /spl mu/m) and low-power (80-mW) 0.18-/spl mu/m CMOS 3.125-Gb/s clock and data recovery circuit is described. The circuit utilizes injection locking to filter out high-frequency reference clock jitter and multiplying delay-locked loop duty-cycle distortions. The injection-locked slave oscillator output can have its output clocks interpolated by current steering the injecting clocks. A second-order clock and data recovery is introduced to perform the interpolation and is capable of tracking frequency offsets while exhibiting low phase wander. |
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