基于CPCI总线控制卡的信号完整性设计

由于CPCI总线的高速数据传输,基于CPCI总线控制卡的设计必须考虑信号完整性问题.从PCB走线、电源和时钟电路3方面进行了信号完整性设计,提出了总线接口芯片9054的PCB走线长度,并给出时钟电源的滤波电路以及电源滤波电容的配置方法.实验结果表明：经过完整性设计的控制卡时钟电路,信号质量明显改善;控制卡电源电压波动小于5％,主机与控制卡通讯速率达到117.97 MByte/s,接近理论极限值.验证了基于CPCI总线控制卡信号完整性设计的正确性.

Signal integrity design on CPCI control card

Because of the CPCI＇s high speed transportation rate,signal integrity must be considered in the design of control card.Signal integrity is designed based on PCB traces,supply and clock circuit.Then PCB trace lengths of bus interface chip 9054,the clock supply filter circuit and the configuration of supply filtering capacitance is proposed.The Experimental results show that the quality of the clock signal is improved significantly through the design of signal integrity,supply voltage variety is less than 5％,communication rates of the host and control card is up to 117.97 MByte/s,closed to the theoretical limit.All above validate that signal integrity design is correct about the CPCI control card.