Profile-based dynamic pipeline scaling |
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Authors: | Kuan-Wei Cheng Tzong-Yen Lin Rong-Guey Chang |
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Affiliation: | (1) Department of Computer Science, National Chung Cheng University, Chia-Yi, Taiwan |
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Abstract: | Low power has played an increasingly important role for embedded systems. To save power, lowering voltage and frequency is
very straightforward and effective; therefore, dynamic voltage scaling (DVS) has become a prevalent low-power technique. However,
DVS makes no effect on power saving when the voltage reaches a lower bound. Fortunately, a technique called dynamic pipeline
scaling (DPS) can overcome this limitation by switching pipeline modes at low-voltage level. Approaches proposed in previous
work on DPS were based on hardware support. From viewpoint of compiler, little has been addressed on this issue. This paper
presents a DPS optimization technique at compiler time to reduce power dissipation. The useful information of an application
is exploited to devise an analytical model to assess the cost of enabling DPS mechanism. As a consequence, we can determine
the switching timing between pipeline modes at compiler time without causing significant run-time overhead. The experimental
result shows that our approach is effective in reducing energy consumption.
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Keywords: | DVS DPS Pipeline mode Loop region IPC |
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