高速数传中定时同步设计与FPGA实现

文中对适用于高速突发通信的基于数字滤波平方的定时同步算法进行了研究。通过对在高速数据传输通信中,该定时同步环路的定时误差估计模块进行并行结构实现,大幅降低了系统对于时钟的要求,且更加易于实现;将文中所提定时控制部分与其他文献中的方法做了对比,表明所用方法可以达到更好的效果。最后进行的Matlab仿真以及硬件实现,结果表明,该环路可以实现突发与非突发情况下的高速数传定时同步。

Design and FPGA Implementation of Timing Synchronization with High-speed Data Transmission

This paper discusses a timing synchronization algorithm based on digital squared filtering which applies for burst communication in the case of high -speed data transmission. First, in the case of high speed data transmission, a parallel structure is used to implement the loop of timing error estimation, which greatly reduces the system requirements for the clock and is easier to implement. A comparison between the proposed timing control circuit and those in other papers indicates that the timing control circuit in this paper is better. Finally, the paper provides Matlab simulation and hardware implementation, whose results show that the loop circuit can realize the timing synchronization efficiently in any case.