Leakage power minimisation in arithmetic circuits

A new approach to the synthesis of arithmetic circuits to minimise leakage power consumption under circuit timing constraint is presented. This is believed to be the first work that addresses the minimisation of leakage power consumption in RTL synthesis of arithmetic circuits. The leakage optimisation is based on the use of dual-threshold voltage (V/sub t/) technology. The proposed approach is performed in two phases: (i) a timing-driven synthesis and placement technique is applied to an arithmetic expression using FA/HA cells with high-V/sub t/ (i.e. slower but lower leakage power than that of low-V/sub t/) to produce a synthesis and placement result with least leakage power consumption; (ii) a technique of minimally replacing the FA/HA cells with high-V/sub t/ from the result in (i) by FA/HA cells with low-V/sub t/ (i.e. more leakage power but faster than that of high-V/sub t/) to meet the timing constraint of the circuit is applied. Experiments using a set of benchmark designs have shown the approach is quite effective, producing designs with on average 34.6% less leakage power over the conventional method without increasing circuit delay.