A Low-Power 100 MHz Analog FIR Filter for PRML Equalization |
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Authors: | Joongho Choi Jungryoul Choi |
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Affiliation: | (1) Department of Electrical Engineering, University of Seoul, 90 Jeonnong-dong, Dongdaemun-gu, Seoul, Korea (, 130-743 |
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Abstract: | This paper presents design of a low-power 100 MHz analog FIR filter for PRML equalization used in the read channel of hard disk drives. The chip consists of 16 channels to provide 15-tap FIR filter operation. By using rotating clocks for sample/hold operation with one dummy channel, timing constraints can be relieved, which results in low-power consumption. The chip incorporates the parallel array of sample-and-hold amplifiers for analog delay line. The sample-and-hold amplifier includes the open-loop unity-gain amplifier with gain-control circuit using replica-biasing scheme, which also improves uniformity among amplifiers. It was fabricated in a 0.8-m CMOS technology and consumes power of 200 mW for V power supply voltage. |
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Keywords: | analog FIR filter PRML equalizer sample-and-hold amplifier gain-control circuit |
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