| 嵌入式系统芯片的软硬件协同仿真环境设计 |
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| 引用本文： | 官枫林,习友宝,刘斌. 嵌入式系统芯片的软硬件协同仿真环境设计[J]. 单片机与嵌入式系统应用, 2011, 11(11): 5-7 |
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| 作者姓名： | 官枫林 习友宝 刘斌 |
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| 作者单位： | 1. 电子科技大学电子工程学院,成都,610000
2. 海思半导体成都研究所 |
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| 摘 要： | 针对嵌入式系统芯片SoC开发验证阶段的需求，介绍了一种通用的SoC软硬件协同仿真平台。软件仿真由C／C＋＋和汇编语言编写，硬件仿真基于VMM验证方法学所搭建，SoC设计代码由RTL代码编写而成。将SoC设计代码中的ARM由DSM模型替代，通过VCS编译器将软硬件协同起来进行信息交互，实现一种速度快、真实性高、调试方便的...
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| 关 键 词： | 协同仿真 DSM模型 验证方法学 片上系统 |
Hardware/Software Co-verification Platform for Embedded Chip |
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| Guan Fenglin,Xi Youbao,Liu Bin. Hardware/Software Co-verification Platform for Embedded Chip[J]. Microcontrollers & Embedded Systems, 2011, 11(11): 5-7 |
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| Authors: | Guan Fenglin Xi Youbao Liu Bin |
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| Affiliation: | 1. School of Electronic Engineering, University of Electronic Science and Technology of China, Chengdu 610000, China; 2. Institute of Hislicon Semiconductor of Chengdu) |
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| Abstract: | With respect to the verification requirement of SoC design, an all purpose co verification platform is presented. Software simulation is written in C/C＋＋ and assembler language. Hardware simulation is based on VMM method. SoC code is written in RTL Verilog. ARM is substituted by DSM model. The simulation process executes communication through VCS. The simulation result verifies that the platform works well. |
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| Keywords: | co-verification DSM VMM SoC |
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