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卷积神经网络RLeNet加速器设计
引用本文:康磊,李慧,郑豪威,李鑫.卷积神经网络RLeNet加速器设计[J].数字社区&智能家居,2021(6).
作者姓名:康磊  李慧  郑豪威  李鑫
作者单位:西安石油大学计算机学院
摘    要:针对卷积神经网络(CNN)对运算的需求,现场可编程逻辑门阵列(FPGA)可以充分挖掘CNN内部并行计算的特性,提高运算速度。因此,本文基于FPGA开发平台,从模型优化、参数优化,硬件加速以及手写体数字识别四个方面对CNN的FPGA加速及应用进行研究。提出一种数字识别网络RLeNet,并对网络进行参数优化,卷积运算加速采用脉冲阵列与加法树结合的硬件结构实现,同时使用并行技术和流水线技术优化加速,并使用microblaze IP通过中断控制CNN加速器IP接收串口发送的图片数据进行预测,输出结果。最后在Xilinx Nexys 4 DDR:Artix-7开发板上实现了MNIST数据集手写体数字识别预测过程,当系统时钟为200MHz时,预测一张图片的时间为36.47us。

关 键 词:CNN  FPGA  RLeNet  MNIST  手写体数字识别

Design of RLeNet Accelerator Based on Convolutional Neural Network
KANG Lei,LI Hui,ZHENG Hao-wei,LI Xin.Design of RLeNet Accelerator Based on Convolutional Neural Network[J].Digital Community & Smart Home,2021(6).
Authors:KANG Lei  LI Hui  ZHENG Hao-wei  LI Xin
Affiliation:(School of Computer Science,Xi'an Shiyou University,Xi'an 710000,China)
Abstract:In response to the requirement of convolutional neural network(CNN)for multiplication and accu-mulation operations,Field Programmable Logic Gate Array(FPGA)can fully tap the characteristics of parallel computing within CNN and increase the speed of operation.Therefore,based on the FPGA development platform,this article studies the FPGA acceleration and application of CNN from four aspects:model optimization,parameter optimization,hardware acceleration,and handwritten digit recognition.Propose a digital recognition network RLeNet,and optimize the parameters of the network.Convolution operation acceleration use a hardware structure combining pulse array and addition tree,parallel technology,pipeline technology,and microblaze IP is used to control the CNN accelerator through interrupts.The IP receives the picture data sent by the serial port for prediction and outputs the result.Finally,on the Xilinx Nexys 4 DDR:Artix-7 development board,the MNIST data set handwritten digit recognition and prediction process is implemented.When the system clock is 200MHz,the time to predict a picture is 36.47us.
Keywords:CNN  FPGA  RLeNet  MNIST  handwritten digit recognition
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