Power-delay-area efficient modulo 2/sup n/+1 adder architecture for RNS |
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Authors: | Patel R.A. Benaissa M. Boussakta S. Powell N. |
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Affiliation: | Dept. of Electron. & Electr. Eng., Univ. of Sheffield, UK; |
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Abstract: | A new modulo 2/sup n/+1 adder architecture based on the ELM addition algorithm is introduced. A simplification to an existing modulo 2/sup n/+1 addition algorithm is also presented. VLSI implementations using 130 nm CMOS technology demonstrate the superiority of the proposed adder over existing designs in the literature. |
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