A 533-MHz BiCMOS superscalar RISC microprocessor |
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| Authors: | Maier CA Markevitch JA Brashears CS Sippel T Cohen ET Blomgren J Ballard JG Pattin J Moldenhauer V Thomas JA Taylor G |
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| Affiliation: | Exponential Technol., San Jose, CA; |
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| Abstract: | This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm×10 mm die contains 2.7 M transistors (2M CMOS and 0.7 M bipolar) and dissipates less than 85 W. The die is fabricated in a six-level metal, 0.5-μm BiCMOS process and requires 3.6 and 2.1 V power supplies |
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