A novel low power and high speed double edge explicit pulse triggered level converter flip‐flop

One of the effective ways to reduce power consumption is using clustered voltage scaling technique. The level converter flip‐flop is needed to control static current when the block with Low Supply Voltage (VDDL) drives the block with High Supply Voltage (VDDH). One of the big challenges of design is that level converter flip‐flop has low power and high speed. In this paper, pulse triggered level converter flip‐flop and double edge pulse generator were proposed. This level converter flip‐flop used conditional data mapping technique for reducing power consumption. An explicit double edge pulse generator could be shared among several level converter flip‐flops so that power consumption would be reduced. Also, the number of stack transistor was reduced in the discharging path that causes delay decrease. The simulation results showed that the proposed flip‐flop reduced 20% of power consumption and 17% of delay in comparison with other flip‐flops at 50% data switching activity. Copyright © 2013 John Wiley & Sons, Ltd.