A Non-Scan Approach to DFT for Controllers Achieving 100% Fault Efficiency |
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Authors: | Satoshi Ohtake Toshimitsu Masuzawa Hideo Fujiwara |
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Affiliation: | (1) Universiti Teknologi Malaysia, 81310 UTM, Skudai, Johor, Malaysia;(2) Osaka Gakuin University, 2-36-1 Kishibe-minami, Suita, Osaka 564-8511, Japan |
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Abstract: | This paper presents a non-scan design-for-testability method for controllers that are synthesized from FSMs (Finite State Machines). The proposed method can achieve complete fault efficiency: test patterns for a combinational circuit of a controller are applied to the controller using state transitions of the FSM. In the proposed method, at-speed test application can be performed and the test application time is shorter than previous methods. Moreover, experimental results show the area overhead is low. |
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Keywords: | non-scan design for testability complete fault efficiency controllers at-speed test |
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