同步和异步时序逻辑电路统一设计的新方法

介绍了一种新的时序电路的设计理论与方法,实现了同步、异步电路的设计过程的统一。该方法的特点是直接从时序电路的状态转换图(STD)获得触发器的激励条件和时钟脉冲;设计原理简单,易于理解,使设计更直观清楚,比传统方法简便、快捷,避免了对状态方程、驱动方程的复杂计算;该设计方法过程可以采用程序实现,实现了时序电路设计的程序化、自动化。

A New Method for Designing Asynchronous and Synchronous Sequential Logic Circuits

In this paper,A new method and theory for desig ni ng asynchronous sequential circuits and synchronous se-quential circuits is put forward.The characteristic of the method is that driving condition and clock pulse for flip-flops are obtained at first hand by means of the state transitio n drawing(STD)and that designing asynchronous sequential cir-cuits and synchr onous sequential circuits can be unified.The method is that designing theory is simpleness and being understood is easy and avoiding complexity computation on state equations and drive equations.Sequential logic circuits design can be rea lized with programming.