基于FPGA实现的星载SAR实时成像系统研究

针对星载SAR实时成像处理的研究目前主要集中在实时成像运算器(SAR processor),而未见到实时成像系统(SAR imaging system)的研究,提出了一种CS算法的星载SAR实时成像系统的体系结构,并基于FPGA实现了原型系统,该体系结构可以自主完成星载SAR实时成像,并具有良好的可扩展性,利用模拟信号源和高速数据记录仪对原型系统验证,1个信号处理单元在50MHz工作频率下,约11s内完成16384×16384个样本的星载雷达原始数据的成像处理,用4个信号处理单元就可达到为PRF为2000Hz的星载SAR的1:1实时成像要求.

FPGA-Based Real-Time Imaging System for Spaceborne SAR

With the rapid development pace of the SAR (synthetic aperture RADAR, SAR) missions, the demands for high data bandwidth of the satellite downlink are required. Reducing the data volume is the necessary task for the SAR missions. On-board SAR image processing has been one of the methods for effective reduction in data volume, since the SAR image data can be compressed much more easily than the SAR raw data. In recent years, FPGA-based real-time imaging for spaceborne SAR is an active research field. The goal of this research work is to design an FPGA-based system which can implement the real-time spaceborne SAR image processing. The parameters of spaceborne SAR are studied. Then a novel high-performance scalable architecture is proposed, which maps the CS (chirp scaling, CS) algorithm to the hardware system, through the analysis of the performance requirements and algorithm specifications. The prototype system implementation and functional verification are also presented. Experiment results show that with one signal processing unit that works at 50MHz, the system can process 512MB SAR raw data within about 11 seconds. The system has attractive merits on high performance and low mass, and is an excellent candidate for the real-time on-board SAR image processing system.