| 一种减少杂散的直接数字频率合成器改进结构 |
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| 引用本文： | 单鸣,李元,谈宜育.一种减少杂散的直接数字频率合成器改进结构[J].微电子学,2002,32(2):117-119,123. |
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| 作者姓名： | 单鸣 李元 谈宜育 |
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| 作者单位： | 南京大学,电子科学与工程系,江苏,南京,210093 |
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| 摘 要： | 直接数字式频率合成器（DDS）是一种全数字器件，它不可避免地会引入杂散信号。杂散多且较难预知一直是限制DDS应用的主要因素，文章对DDS的杂散进行了分析，并采用Verilog HDL，设计了一种减少杂散的DDS改进结构，Matalab分析结果表明，所设计的DDS杂散波明显减少，信噪比提高36dB。
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| 关 键 词： | 直接数字式频率合成器 相位截断误差 Verilog HDL DDS |
| 文章编号： | 1004-3365(2002)02-0117-03 |
An Improved Direct Digital Synthesizer with Reduced Spurious Noise |
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| SHAN Ming,LI Yuan,TAN Yi yu.An Improved Direct Digital Synthesizer with Reduced Spurious Noise[J].Microelectronics,2002,32(2):117-119,123. |
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| Authors: | SHAN Ming LI Yuan TAN Yi yu |
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| Abstract: | Direct digital frequency synthesizer (DDS) is a digital system, so it inevitably has spurious noise, which is the key factor limiting the application of DDS In this paper, an analysis of the spurious noise in DDS is made An improved DDS structure with reduced spurious noise is designed by using Verilog HDL language Simulation by Matlab indicates that the spurious noise in the DDS decreases evidently, and the signal to noise ratio (SNR) is increased by 36 dB |
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| Keywords: | Direct digital frequency synthesizer Frequency synthesis Phase truncation error Verilog HDL |
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