显式并行资源计算结构及其编译优化

提出并分析了一种新的基于超长指令字(VLIW)思想的微处理器模型,该模型提供了体系结构可见的处理器内部结果寄存器和数据通路,允许优化编译器进行直接的控制和调度,并依赖编译器保证操作之间的依赖关系,以简化硬件设计并获得更高的时钟频率.基于该目标模型,构造了一个完整的优化编译和模拟环境,提出、分析并实现了相应的软件旁路优化以及集成式的资源分配与指令调度算法.

Explicit Parallelism Resource Computing and Compiler Optimizations

A new micro-processor machine model, based on very long instruction word, is proposed and analyzed. This model not only provides architecture visible result registers and data paths inside the processor, which allow optimizing compiler to control and schedule them directly, but also depends on compiler to guarantee the correct dependency among the operations, aiming at simplifying hardware design and achieving high clock frequency. For this target model, a complete compiling, optimizing and simulating environment is constructed. Corresponding optimizing algorithms, such as software bypass and integrated resource allocation and instruction scheduling are proposed, analyzed and implemented.