| 适合实时硬件实现的Bayer图像插值算法 |
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| 引用本文： | 郭建亚,徐智勇.适合实时硬件实现的Bayer图像插值算法[J].仪器仪表用户,2011,18(5):67-71. |
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| 作者姓名： | 郭建亚 徐智勇 |
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| 作者单位： | 1. 中国科学院光电技术研究所,成都610209;中国科学院研究生院,北京100190
2. 中国科学院光电技术研究所,成都,610209 |
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| 摘 要： | 现今已有大量的CFA插值算法问世,然而大多数只是针对独立使用或者是后期处理的场合。因为这些方法往往需要复杂的运算过程甚至迭代计算,所以不适合实时硬件实现。针对高清Bayer图像,提出了一种面向硬件的实时、高效的插值算法。该算法专注于插值过程的计算复杂度最小化以适合低资源利用量的实时硬件实现并且使最终输出的彩色图像保持较高的质量。使用加权梯度方法对每个像素的3乘5邻域分析得到最平滑的两个方向,丢失的两个颜色分量则沿该两个方向进行插值。采用了峰值信噪比(PSNR)和CIELAB颜色空间误差两种评判标准将该算法与目前一些常用的插值算法进行了比较。
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| 关 键 词： | Bayer阵列 去马赛克 插值 高清 实时 流水线 硬件实现 FPGA |
A Bayer CFA demosaicing method suitable for real-time hardware implementation |
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| GUO Jian-ya,XU Zhi-vong.A Bayer CFA demosaicing method suitable for real-time hardware implementation[J].Electronic Instrumentation Customer,2011,18(5):67-71. |
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| Authors: | GUO Jian-ya XU Zhi-vong |
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| Affiliation: | GUO Jian-ya1,2,XU Zhi-yong1 (1.Institute of Optics and Electronics,Chinese Academy of Sciences,Chengdu 610209,China,2.Graduate University of Chinese Academy of Sciences,Beijing 100190,China) |
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| Abstract: | There are currently a lot of methods available for CFA demosaicing,however most of them are designed for off-line or post-processing purpose,requiring complex computing process or even iterations which are not suitable for real time hardware implementation.In this paper,a cost effective method for high definition Bayer pattern image demosaicking dedicated to compact hardware implementation is proposed.In order to reduce the time and resources required for hardware implementation,the proposed method focus on... |
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| Keywords: | Bayer CFA demosaicing interpolation high definition real-time pipeline hardware implementation FPGA |
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